1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method of the same, and in particular, to a structure of a memory cell of an SRAM (Static Random Access Memory) and a manufacturing method of the same.
2. Description of the Background Art
SRAMs are one type of known semiconductor memory devices. FIG. 25 is an equivalent circuit diagram showing one memory cell of a conventional SRAM. This memory cell is formed of six transistors including P-type MOS transistors as a load. Specifically, a pair of driver transistors Q.sub.1 and Q.sub.2 (N-type MOS transistors) and a pair of load transistors Q.sub.5 and Q.sub.6 (P-type MOS transistors) are mutually connected to form a flip-flop circuit. A pair of the load transistors Q.sub.5 and Q.sub.6 have source regions 110 and 111 connected to a V.sub.cc power supply. The driver transistors Q.sub.1 and Q.sub.2 have source regions connected to GNDs 112 and 113, respectively. A pair of access transistors Q.sub.3 and Q.sub.4 (N-type MOS transistors) are connected to memory nodes 114 and 115, respectively. A bit line 107 is connected to one of source/drain regions of the access transistor Q.sub.3. A bit line 108 is connected to one of source/drain regions of the access transistor Q.sub.4. Gate electrodes of the access transistors Q.sub.3 and Q.sub.4 are connected to a word line 109.
FIGS. 26-28 are plans of a memory cell of the SRAM, and show structures of lower, middle and upper layers on and above a surface of a substrate, respectively. FIG. 29 is a cross section taken along line 29--29 in FIGS. 26-28. Referring to FIGS. 25-29, the conventional memory cell includes a silicon substrate 148 having a main surface, on which a pair of the driver transistors Q.sub.1 and Q.sub.2 as well as a pair of the access transistors Q.sub.3 and Q.sub.4 are formed. The driver transistor Q.sub.1 has a drain region 121, a source region 122 and a gate electrode 125. The driver transistor Q.sub.2 has a drain region 117, a source region 118 and a gate electrode 126.
The access transistor Q.sub.3 has a pair of source/drain regions 119 and 120 as well as a gate electrode 109. The access transistor Q.sub.4 has a pair of source/drain regions 116 and 117 as well as a gate electrode 109.
These transistors are formed of N-type MOS transistors having source/drain regions which are formed in the main surface of the P-type silicon substrate 148. The gate electrode 126 of the driver transistor Q.sub.2 is connected to the source/drain region 120 of the access transistor Q.sub.3 through a contact portion 128. The gate electrode 126 of the driver transistor Q.sub.2 is connected to the drain region 121 of the driver transistor Q.sub.1 through a contact portion 129. The gate electrode 125 of the driver transistor Q.sub.1 is connected to the source/drain region 117 of the access transistor Q.sub.4 and the drain region 117 of the driver transistor Q.sub.2 through a contact portion 127.
A gate electrode 130 of the load transistor Q.sub.5 is connected through a contact portion 139 to a source/drain region 137 of the load transistor Q.sub.6. A gate electrode 131 of the load transistor Q.sub.6 is connected through a contact portion 138 to source/drain region 134 of the load transistor Q.sub.5.
The bit line 107 is connected through a contact portion 146 to the source/drain region 119 of the access transistor Q.sub.3. The bit line 108 is connected through a contact portion 147 to the source/drain region 116 of the access transistor Q.sub.4.
As described above, the memory cell of the SRAM in the prior art includes the four N-type MOS transistors disposed on the silicon substrate, and the thin-film transistor of P-type disposed in the upper layer and used as a load. FIG. 30 is a cross section showing a typical example of a thin-film transistor which can be used as the load transistors Q.sub.5 and Q.sub.6. Referring to FIG. 30, the thin-film transistor includes a semiconductor layer, e.g., of polysilicon, in which a channel region 142 and a pair of source/drain regions 141 and 143 are formed. A gate electrode 140 is disposed at a position opposed to the channel region 142 with an insulating layer therebetween. FIG. 31 shows a current characteristic of the foregoing thin-film transistor. In this figure, "Vd" represents a drain voltage, "Vg" represents a gate voltage, and "Id" represents a drain current.
FIG. 32 is an equivalent circuit diagram showing a read operation of the memory cell of the SRAM. Referring to FIG. 32, the load transistors Q.sub.5 and Q.sub.6 shown in FIG. 25 are not shown in this equivalent circuit diagram because the current flowing therethrough is sufficiently small. The bit lines 107 and 108 are connected to bit line loads 160 and 161 formed of P-type MOS transistors.
It is assumed that a memory node A is at L level, and a memory node B is at H level. In the read operation, the current i flows from the bit line load 160 through the memory node A at the L level to the GND 112. Meanwhile, in connection with the memory node B at the H level, the current does not flow from the bit line load 161 to the GND 113.
As shown in FIG. 26, the source region 122 of the driver transistor Q.sub.1 and the source region 118 of the driver transistor Q.sub.2 are formed at different regions. Parasitic resistances r are formed between the source region 118 and GND 113 and between the source region 122 and GND 112. In the state shown in FIG. 32, therefore, the potential of a node C increases by r.times.i. Meanwhile, the current does not flow through a node D, so that the potential of the node D does not increase. Therefore, the potentials of the nodes C and D in one memory cell become unbalanced, and thus the correct read operation cannot be executed. In other words, when the potential of the node C increases, the potential of the memory node A also increases, resulting in a disadvantage that the potential of the memory node A changes from the L level to the H level, and the potential of the memory node B changes from the H level to the L level. In this case, erroneous data is read in the data read operation.
The following disadvantage is also caused. FIG. 33 is a cross section of a structure in which the first direct contact portions 127, 128 and 129 shown in FIGS. 26 and 29 have shared direct contact structures. The shared contact structures shown in FIG. 33 have been frequently used in the prior art. Specifically, the gate electrode 126 of the driver transistor Q.sub.2 is formed on an element isolating oxide film 124 with a gate oxide film 162 therebetween. An interlayer insulating film 164 is formed on the silicon substrates 148 and the gate electrode 126. A contact hole 164a is formed in the layer insulating film 164 located between the gate electrode 126 and the drain region 121 of the driver transistor Q.sub.1. The gate electrode 126 and the drain region 121 are electrically connected to each other in the contact hole by a second polysilicon layer 165. Although the shared direct contact portion 163 is formed in this manner, a following disadvantage occurs if a position of the end portion of the gate electrode 126 deviates. FIG. 34 is a cross section showing the disadvantage caused by the deviation of the end portion of the gate electrode 126 of the driver transistor Q.sub.2. As shown in FIG. 34, if the end portion of the gate electrode 126 is located above the element isolating oxide film 124, the end portion of the element isolating oxide film 124 is shaved due to an etching process for forming the contact hole 164a. This results in a disadvantage that a leak current i.sub.0 is generated at a position where the element isolating oxide film 124 is shaved.
Further, the following disadvantage is caused. FIG. 35 is an enlarged fragmentary cross section of the load transistor Q.sub.6 shown in FIG. 29. Referring to FIG. 35, the potential of the bit line 107 changes in an actual operation. Therefore, the bit line 107 acts as a gate electrode of the load transistor Q.sub.6, resulting in malfunction of the load transistor Q.sub.6. This phenomenon has been referred to as a crosstalk phenomenon.